1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device capable of readily distinctively forming a transistor in a memory cell part and transistors in a peripheral circuit part while reducing the number of times of high-temperature heat treatment.
2. Description of the Background Art
Referring to FIG. 34, a conventional nonvolatile semiconductor memory device is divided into a memory cell part R1 and a peripheral circuit part R2 located in the periphery thereof. A memory cell transistor 150 is arranged on the memory cell part R1 while two types of transistors 161 and 162 are arranged on the peripheral circuit part R2. The difference between the two types of transistors 161 and 162 resides in difference between the thicknesses of gate insulator films 127 and 137, as described later.
FIG. 34 shows the memory transistor 150 of the memory cell part R1 in two sections along bit and word lines respectively. An n-conductivity type bottom well 103 is provided at a part of the bottom of a silicon substrate 101 formed in the memory cell part R1 isolated from the peripheral circuit part R2 by an element isolation zone 102. A p-conductivity type well 105 is formed at the n-conductivity type bottom well 103. The memory cell transistor 150 has source and drain regions 108a and 180b formed in the p-conductivity type well 105 and a gate insulator film 106 arranged on the silicon substrate 101. A floating gate 107 enclosed with an insulating region 109 is arranged on the gate insulator film 106. An inter-gate isolation film 110 consisting of a three-layer insulator film including a silicon oxide film, a silicon nitride film and a silicon oxide film is formed on the floating gate 107. A control gate 113 is arranged on the inter-gate isolation film 110. A layer 114 of WSi and an insulator film 115 are arranged on the control gate 113.
An n-conductivity type well 104 and a p-conductivity type well 105 are provided on the peripheral circuit part R2. The two types of transistors 161 and 162 are provided in each of the wells 104 and 105. The transistor 161 has a gate oxide film 127, and the transistor 162 has a gate oxide film 137 having a larger thickness than the gate oxide film 127. Conductive layers 113 of the same perpendicular structure as the control gate 113, WSi films 114 and insulator films 115 are provided on the gate oxide films 127 and 137 respectively. In the peripheral circuit part R2, the transistors 161 and 162 include low-concentration impurity regions 116 and 117 provided on the silicon substrate 101 and high-concentration impurity regions 119 and 120 formed by implanting an impurity through masks defined by side wall spacers provided on the side surfaces of gate electrodes. Plug wires 125 conductive with wires 126 arranged on an interlayer dielectric film 124 are connected to the high-concentration impurity regions 119 and 120.
A method of fabricating the conventional nonvolatile semiconductor memory device is now described with reference to FIGS. 35 to 43.
First, the element isolation zone 102 is formed on the main surface of the p-conductivity type silicon substrate 101 having  less than 100 greater than crystal orientation (see FIG. 35). Then, a resist pattern is formed on the main surface of the silicon substrate 101 as a mask for ion-implanting phosphorus into the memory cell part R1 with acceleration energy of 3 MeV and density of 1.0E13, for example, thereby forming the n-conductivity type bottom well region 103, and the resist pattern is removed. In the following description, processing of removing a resist film is not described.
Then, phosphorus is ion-implanted into the region of the peripheral circuit part R2 to be formed with p-conductivity type MOS (metal oxide semiconductor) transistors with acceleration energy of 1.2 MeV and density of 1.0E13, for example, through a resist pattern serving as a mask. Further, phosphorus for channel cutting and boron for counter doping are ion-implanted into the same region with 700 keV and 3.0 E 12 and with 20keV and 1.5 E12 respectively, for example. The n-conductivity type well region 104 is formed by this ion implantation (see FIG. 35).
Then, the p-conductivity type well regions 105 are formed in the region of the peripheral circuit part R2 to be formed with n-conductivity type MOS transistors and a region of the memory cell part R2 to be formed with a memory cell through a resist pattern serving as a mask in the following three stages (a), (b) and (c) (see FIG. 35): (a) Boron is ion-implanted with acceleration energy of 700 keV and density of about 1.0E13, for example. (b) Boron for p-channel cutting is ion-implanted with acceleration energy of 270 keV and density of 3.5E12, for example. (c) Boron for channel doping is ion-implanted with acceleration energy of 50 keV and density of 1.2E12, for example.
Thereafter a silicon oxide film 106 of about 10 nm in thickness is formed on the main surface of the silicon substrate 101 by thermal oxidation. Then, a phosphorus-doped polycrystalline silicon film 107 of about 200 nm in thickness is formed. Thereafter a resist pattern is formed on the overall main surface of the silicon substrate 101 by photolithography. This resist pattern is employed as a mask for patterning the phosphorus-doped polycrystalline silicon film 107 thereby forming the floating gate 107 on the region to be formed with the memory transistor 150.
Then, arsenic is ion-implanted into the region of the silicon substrate 101 to be formed with the memory cell with acceleration energy of 35 keV and density of about 3.0E15, for example, through a resist pattern serving as a mask for forming n-conductivity type impurity diffusion regions as the source and drain regions 108a and 108b. Thereafter a silicon oxide film 109 of 800 nm in thickness is deposited on the silicon substrate 101 by low-pressure CVD (chemical vapor deposition). The overall surface of this silicon oxide film 109 is etched thereby exposing the surface of the phosphorus-doped polycrystalline silicon film 107 (see FIG. 35).
Then, the three-layer insulator film 110 is formed on the main surface of the silicon substrate 101. In formation of the three-layer insulator film 110, a silicon oxide film of 5 nm in thickness is first formed by thermal oxidation. Then, a silicon nitride film of 10 nm in thickness is formed thereon by low-pressure CVD. Further, another silicon oxide film of 5 nm in thickness is formed thereon by low-pressure CVD, thereby defining the three-layer insulator film 110.
Thereafter a resist pattern is formed on the silicon substrate 101 by photolithography. This resist pattern is employed for patterning the three-layer insulator film 110, the phosphorus-doped polycrystalline silicon film 107 and the gate oxide film 106 on the peripheral circuit part R2, as shown in FIG. 35.
Thereafter silicon oxide films 111 of about 20 nm in thickness are formed on the regions of the peripheral circuit part R2 to be formed with thick gate insulator films, i.e., to be formed with high withstand voltage transistors. At this time, the silicon nitride film included in the three-layer insulator film 110 prevents the underlayer from thermal oxidation in the memory cell part Rd. Then, resist patterns are formed on the regions of the peripheral circuit part R2 to be formed with the high withstand voltage transistors and the memory cell part R1 by photolithography for patterning the silicon oxide films 111 in regions of the peripheral circuit part R2 to be formed with low withstand voltage transistors (FIG. 36).
A silicon oxide film 127 of about 10 nm for defining the gate oxide films of the low withstand voltage transistors of the peripheral circuit part R2 is grown on the silicon substrate 101 by thermal oxidation. At this time, the silicon nitride film included in the three-layer insulator film 110 prevents the underlayer from thermal oxidation in the memory cell part R1. On the other hand, a silicon oxide film 137 for defining the gate oxide films of the high withstand voltage transistors of the peripheral circuit part R2 is larger than 20 nm and smaller than 30 nm in thickness. Then, a phosphorus-doped polycrystalline silicon film 113 of about 200 nm in thickness, a WSi film 114 of about 100 nm in thickness and a silicon oxide film 115 of about 200 nm in thickness are successively deposited in ascending order. Thereafter a resist pattern is formed by photolithography and employed as a mask for patterning the silicon oxide film 115. The patterned silicon oxide films 115 are employed as masks for patterning the WSi film 114 and the phosphorus-doped polycrystalline silicon film 113 (FIG. 37).
Thereafter the phosphorus-doped polycrystalline silicon film 113, the WSi film 114 and the silicon oxide film 115 of about 200 nm in thickness in the memory cell part R1 of the silicon substrate 101 are employed as masks for patterning the three-layer insulator film 110 and the phosphorus-doped polycrystalline silicon film 107 (FIG. 38).
Then, phosphorus is ion-implanted into the region of the silicon substrate 101 to be formed with n-conductivity type MOS transistors of the eripheral circuit part R2 with acceleration energy of 50 keV and density of about 4.0E13 through a resist pattern serving as a mask. Thus, the low-concentration impurity regions 116 of the n-conductivity MOS transistors of the peripheral circuit part R2 are formed (FIG. 39).
Then, boron is ion-implanted into the region of the silicon substrate 101 to be formed with p-conductivity type MOS transistors of the peripheral circuit part R2 with acceleration energy of 50 keV and density of about 1.5E13 through a resist pattern serving as a mask. Thus, the low-concentration impurity regions 117 of the p-conductivity type MOS transistors are formed in the peripheral circuit part R2 (FIG. 40). A silicon oxide film of about 100 nm is formed on the silicon substrate 101 by CVD. Then, side wall spacers 123 are formed by anisotropic etching (FIG. 41).
Then, arsenic is ion-implanted into the region of the silicon substrate 101 to be formed with the n-conductivity type MOS transistors of the peripheral circuit part R2 with acceleration energy of 35 keV and density of about 4.0E15, for example, through a resist pattern serving as a mask.
Thus, the high-concentration impurity regions 119 of the n-conductivity type MOS transistors are formed (FIG. 42).
Further, BF2 is ion-implanted into the region of the silicon substrate 101 to be formed with the p-conductivity type MOS transistors of the peripheral circuit part R2 with acceleration energy of 20 keV and density of 2.0E15, for example, through a resist pattern serving as a mask. Thus, the high-concentration impurity regions 120 of the p-conductivity type MOS transistors are formed (FIG. 43). Thereafter wires are formed through general wire formation. The conventional nonvolatile semiconductor memory device is fabricated through the aforementioned method.
In the nonvolatile semiconductor memory device, a high voltage VPP of about 20 V is generally applied to the control gate 113 while grounding the n-conductivity type diffusion regions 108a and 108b and the silicon substrate 101 in program formation. Thus, electrons are generated in a channel formed between the n-conductivity type diffusion layers 180a and 108b. These electrons tunnel through an energy barrier formed by the tunnel insulator film 106 and are injected into the floating gate 107. Consequently, the threshold voltage of the memory cell is increased.
In program erasing, a high voltage VPP of aboutxe2x88x9220 V is generally applied to the control gate 113 while grounding the n-conductivity type diffusion regions 108a and 108b and the silicon substrate 101. Tunneling results from this circuit formation, to discharge electrons from the floating gate 107 to the silicon substrate 101. Consequently, the threshold voltage of the memory cell is reduced.
In a read operation of a selected memory transistor, voltages of 3.3 V (Vcg=3.3 V) are applied to the control gate 113 and the drain 108a of the n-conductivity type diffusion layer while grounding the source 108b of the n-conductivity type diffusion layer and the silicon substrate 101. Assuming that Vthp  greater than 3.3 V  greater than Vthe, no current flows between the source 108b and the drain 108a of the memory transistor in a reading state while a current flows in a program erasing state.
In reading, the control gate 113 is grounded (Vcg=0 V), a voltage of 3.3 V is applied to the drain 108a of the n-conductivity type diffusion region, and the source 108b of the n-conductivity type diffusion region and the silicon substrate 101 are grounded in a non-selected transistor. Assuming that Vthp  greater than Vthe  greater than 0 V, no current flows between the source 108b and the drain 108a of the memory transistor if the voltage Vcg is 0 V.
A current flows between the source 108b and the drain 108a only in a memory transistor of a program reading state among selected ones, so that information can be detected from each memory cell.
Therefore, the peripheral circuit part R2 of the nonvolatile semiconductor memory device requires two types of transistors, i.e., (1) a low withstand voltage transistor having a thin gate oxide film with high current drivability for increasing the speed for the reading operation and (2) a high withstand voltage transistor having a gate oxide film capable of withstanding a high applied voltage.
In the conventional fabrication method, however, the memory cell transistor and the two types of transistors having gate oxide films of different thicknesses in the peripheral circuit part must be formed independently of each other. Therefore, high-temperature heat treatment must be performed a number of times for forming the gate oxide films with a long time. This leads to the following problems:
(1) The number of thermal oxidation steps requiring a high cost is increased.
(2) Diffusion regions formed by ion implantation are spread due to exposure to high-temperature heat treatment over a long time, to inhibit refinement of semiconductor elements.
(3) The number of high-temperature heat treatment steps is so large that stress is applied to a portion of the silicon substrate 101 around the element isolation zone 102 due to difference between the thermal expansion coefficients of the silicon oxide film and the silicon substrate 101 to cause crystal defects in the silicon substrate 101.
An object of the present invention is to provide a nonvolatile semiconductor memory device and a method of fabricating the same capable of distinctively forming transistors of a peripheral circuit part and a memory cell part while minimizing the number of times of high-temperature heat treatment, particularly capable of readily distinctively forming a high withstand voltage transistor and a low withstand voltage transistor directed to improvement of the operating speed in the peripheral circuit part.
The nonvolatile semiconductor memory device according to the present invention comprises a memory cell part and a peripheral circuit part located in the periphery of the memory cell part on a semiconductor substrate. The memory cell part includes a memory cell transistor having a floating gate located on a gate insulator film, an inter-gate isolation film located on the floating gate and a control gate located on the inter-gate isolation film. The peripheral circuit part includes a first transistor including a first gate insulator film and a second transistor including a second gate insulator film. In this nonvolatile semiconductor memory device, at least one of the first and second transistors includes a lower conductive layer, an intermediate insulator film and an upper conductive layer located in ascending order on the gate insulator film in contact with each other. The lower conductive layer has the same perpendicular structure as the floating gate, the intermediate insulator film includes an insulator film of the same perpendicular structure as the inter-gate isolation film, and the upper conductive layer has the same perpendicular structure as the conductive layer of the control gate. Further, the intermediate insulator film includes a conduction part electrically connecting the upper conductive layer and the lower conductive layer with each other.
According to this structure, the floating gate, and the control gate isolated from each other by the isolation film in the memory cell part can be electrically connected with each other in the peripheral circuit part. In the peripheral circuit part, therefore, either one of the floating gate and the control gate can be employed as a gate electrode. Therefore, (A) a gate portion of the nonvolatile transistor of the memory cell part and gate portions of the transistors of the peripheral circuit part can be simultaneously formed in the same perpendicular structure, for reducing the number of fabrication steps. Further, for example, (B) the number of the fabrication steps can be further reduced by simultaneously forming a gate oxide film of the nonvolatile transistor and a gate oxide film of the first transistor, for example, of the peripheral circuit part in common with the same peripheral structure. Consequently, (B1) thermal oxidation can be suppressed for suppressing crystal defects in the semiconductor substrate. Further, heat history applied to the semiconductor substrate is so reduced that (B2) impurity diffusion regions are not enlarged in size, not to inhibit the nonvolatile semiconductor memory device from miniaturization.
In general, the aforementioned first and second transistors are classified into a high withstand voltage transistor and a transistor directed to a high-speed operation with no requirement for high voltage resistance respectively. In other words, first and second gate oxide films are different in thickness from each other. However, the present invention is not necessarily restricted to the aforementioned classification but another classification may alternatively be employed. The aforementioned first and second transistors are formed in each of n- and p-conductivity type wells.
The wording xe2x80x9clower conductive layer having the same perpendicular structure as the floating gatexe2x80x9d indicates that the same layer as the floating gate is formed on the peripheral circuit part in formation of the floating gate and employed as the lower conductive layer. This also applies to the remaining layers. When two layers have the same perpendicular structure, therefore, the layers are identical in (a) perpendicular size and (b) perpendicular chemical composition distribution to each other.
Each of the first and second transistors includes the lower conductive layer of the same perpendicular structure as the floating gate, the intermediate insulator film including the insulator film of the same perpendicular structure as the inter-gate isolation film and the upper conductive layer of the same perpendicular structure as the control gate on the gate insulator film.
The first transistor includes the lower conductive layer of the same perpendicular structure as the floating gate, the intermediate insulator film including the insulator film of the same perpendicular structure as the inter-gate isolation film and the upper conductive layer of the same perpendicular structure as the control gate on the first gate insulator film. The second transistor can include a conductive layer of the same perpendicular structure as the control gate on the second gate insulator film.
Also according to this structure, functions/effects identical to the above inventive functions/effects (A), (B), (B1) and (B2) can be attained.
The method of fabricating a nonvolatile semiconductor memory device according to the present invention comprises steps of forming a lower insulator film on a region of the peripheral circuit part on the semiconductor substrate formed with the second transistor, forming the gate insulator film covering the semiconductor substrate and the lower insulator film, forming a floating conductive layer defining the floating gate on the gate insulator film, forming the inter-gate isolation film on the floating conductive layer, and opening a through hole reaching the floating conductive layer in regions of the inter-gate isolation film formed with the first and second transistors.
According to this method, the gate insulator films of the first transistor and the memory transistor can be simultaneously fabricated in common in the same composition. The thickness of the gate insulator film of the second transistor can be increased beyond that of the gate insulator film of the first transistor by the thickness of the lower insulator film. In the aforementioned method, the gate oxide films of the transistors may not be separately formed for the memory cell part and the peripheral circuit part, whereby thermal oxidation is suppressed. Therefore, crystal defects can be suppressed in the semiconductor substrate. Heat treatment history applied to the semiconductor substrate is suppressed, whereby an impurity diffusion region can be inhibited from spreading, not to inhibit refinement of the nonvolatile semiconductor memory device.
Another method of fabricating a nonvolatile semiconductor memory device according to the present invention comprises a step of successively stacking a gate insulator film, a floating conductive layer for defining the floating gate on the gate insulator film and the inter-gate isolation film on the conductive layer in common to the memory cell part and the peripheral circuit part. The method further comprises steps of partially removing the successively stacked gate insulator film, floating conductive layer and inter-gate isolation film only in the range of regions formed with the second transistor in plan view for exposing the semiconductor substrate and forming the second gate insulator film having a larger thickness than the gate insulator film only on the region of the second transistor. The method further comprises steps of opening a through hole reaching the floating conductive layer in a region of the inter-gate isolation film formed with the first transistor and forming a control conductive layer defining the control gate to fill up the through hole and cover the second gate insulator film over the memory cell part and the peripheral circuit part.
According to this method, the gate oxide films of the first transistor and the memory transistor can be formed through a common step for reducing the number of fabrication steps also when only the first transistor has the insulator film of the same perpendicular structure as the inter-gate isolation film of the memory cell part for the gate electrode and only the upper conductive layer is stacked for the second transistor, thereby reducing the number of steps.